From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 13:32:01 +0000 (+0100) Subject: decide to elaborate Refiles *into* another class, rather than make them their X-Git-Tag: div_pipeline~632 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1668d4ed9b57602324e3c86f0e97de6ee7a739c7;p=soc.git decide to elaborate Refiles *into* another class, rather than make them their own module. this will reduce a level of hierarchy and make access easier --- diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index ee9a7ff8..12456d25 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -19,7 +19,6 @@ Links: # TODO -from nmigen import Elaboratable, Module from soc.regfile.regfile import RegFile, RegFileArray from soc.regfile.virtual_port import VirtualRegPort from soc.decoder.power_enums import SPR @@ -129,7 +128,7 @@ class SPRRegs(RegFile): self.r_ports = [self.read_port("src")] # class containing all regfiles: int, cr, xer, fast, spr -class RegFiles(Elaboratable): +class RegFiles: def __init__(self): self.rf = {} for (name, kls) in [('int', IntRegs), @@ -140,8 +139,7 @@ class RegFiles(Elaboratable): rf = self.rf[name] = kls() setattr(self, name, rf) - def elaborate(self, platform): - m = Module() + def elaborate_into(self, m, platform): for (name, rf) in self.rf.items(): setattr(m.submodules, name, rf) return m