From: Claire Wolf <clifford@clifford.at>
Date: Wed, 29 Jan 2020 16:01:24 +0000 (+0100)
Subject: Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
X-Git-Tag: working-ls180~833
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1679682fa3ae18282b49452891282901a3548ecc;p=yosys.git

Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys

Also some minor fixes to the original PR.
---

1679682fa3ae18282b49452891282901a3548ecc
diff --cc passes/opt/opt_reduce.cc
index 09f6e12e9,8126f3c0d..f74655d1c
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@@ -43,13 -43,14 +43,14 @@@ struct OptReduceWorke
  			return;
  		cells.erase(cell);
  
 -		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 +		RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+ 		sig_a.sort_and_unify();
  		pool<RTLIL::SigBit> new_sig_a_bits;
  
--		for (auto &bit : sig_a.to_sigbit_set())
++		for (auto &bit : sig_a)
  		{
  			if (bit == RTLIL::State::S0) {
 -				if (cell->type == "$reduce_and") {
 +				if (cell->type == ID($reduce_and)) {
  					new_sig_a_bits.clear();
  					new_sig_a_bits.insert(RTLIL::State::S0);
  					break;
@@@ -86,8 -87,9 +87,9 @@@
  		}
  
  		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
+ 		new_sig_a.sort_and_unify();
  
 -		if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
 +		if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
  			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
  			did_something = true;
  			total_count++;