From: Julian Brown Date: Fri, 3 Jun 2011 10:22:52 +0000 (+0000) Subject: gcc/ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16868d849b17f2d34d9499b21b4fb6d5f2bddad9;p=gcc.git gcc/ * config/arm/arm-cores.def (strongarm, strongarm110, strongarm1100) (strongarm1110): Use strongarm tuning. * config/arm/arm-protos.h (tune_params): Add max_insns_skipped field. * config/arm/arm.c (arm_strongarm_tune): New. (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune) (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a5_tune) (arm_cortex_a9_tune, arm_fa726te_tune): Add max_insns_skipped field setting, using previous defaults or 1 for Cortex-A5. (arm_option_override): Set max_insns_skipped from current tuning. From-SVN: r174599 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f11caf80d45..b63f0e0543f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2011-06-03 Julian Brown + + * config/arm/arm-cores.def (strongarm, strongarm110, strongarm1100) + (strongarm1110): Use strongarm tuning. + * config/arm/arm-protos.h (tune_params): Add max_insns_skipped + field. + * config/arm/arm.c (arm_strongarm_tune): New. + (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune) + (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a5_tune) + (arm_cortex_a9_tune, arm_fa726te_tune): Add max_insns_skipped field + setting, using previous defaults or 1 for Cortex-A5. + (arm_option_override): Set max_insns_skipped from current tuning. + 2011-06-03 Nathan Sidwell * doc/install.texi (Options specification): Document --with-specs. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index afac688eb15..11a6ad93b79 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -70,10 +70,10 @@ ARM_CORE("arm7dmi", arm7dmi, 3M, FL_CO_PROC | FL_MODE26, fastmul) /* V4 Architecture Processors */ ARM_CORE("arm8", arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul) ARM_CORE("arm810", arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul) -ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) -ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) +ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul) ARM_CORE("fa626", fa626, 4, FL_LDSCHED, fastmul) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index c104d741d77..67aee46e0bf 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -221,6 +221,9 @@ struct tune_params bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); int constant_limit; + /* Maximum number of instructions to conditionalise in + arm_final_prescan_insn. */ + int max_insns_skipped; int num_prefetch_slots; int l1_cache_size; int l1_cache_line_size; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 57c523840f2..057f9bae9c0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -859,6 +859,7 @@ const struct tune_params arm_slowmul_tune = arm_slowmul_rtx_costs, NULL, 3, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost @@ -869,6 +870,21 @@ const struct tune_params arm_fastmul_tune = arm_fastmul_rtx_costs, NULL, 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + true, /* Prefer constant pool. */ + arm_default_branch_cost +}; + +/* StrongARM has early execution of branches, so a sequence that is worth + skipping is shorter. Set max_insns_skipped to a lower value. */ + +const struct tune_params arm_strongarm_tune = +{ + arm_fastmul_rtx_costs, + NULL, + 1, /* Constant limit. */ + 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost @@ -879,6 +895,7 @@ const struct tune_params arm_xscale_tune = arm_xscale_rtx_costs, xscale_sched_adjust_cost, 2, /* Constant limit. */ + 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost @@ -889,6 +906,7 @@ const struct tune_params arm_9e_tune = arm_9e_rtx_costs, NULL, 1, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost @@ -899,6 +917,7 @@ const struct tune_params arm_v6t2_tune = arm_9e_rtx_costs, NULL, 1, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_default_branch_cost @@ -910,16 +929,21 @@ const struct tune_params arm_cortex_tune = arm_9e_rtx_costs, NULL, 1, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_default_branch_cost }; +/* Branches can be dual-issued on Cortex-A5, so conditional execution is + less appealing. Set max_insns_skipped to a low value. */ + const struct tune_params arm_cortex_a5_tune = { arm_9e_rtx_costs, NULL, 1, /* Constant limit. */ + 1, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_cortex_a5_branch_cost @@ -930,6 +954,7 @@ const struct tune_params arm_cortex_a9_tune = arm_9e_rtx_costs, cortex_a9_sched_adjust_cost, 1, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_BENEFICIAL(4,32,32), false, /* Prefer constant pool. */ arm_default_branch_cost @@ -940,6 +965,7 @@ const struct tune_params arm_fa726te_tune = arm_9e_rtx_costs, fa726te_sched_adjust_cost, 1, /* Constant limit. */ + 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost @@ -1735,12 +1761,7 @@ arm_option_override (void) max_insns_skipped = 6; } else - { - /* StrongARM has early execution of branches, so a sequence - that is worth skipping is shorter. */ - if (arm_tune_strongarm) - max_insns_skipped = 3; - } + max_insns_skipped = current_tune->max_insns_skipped; /* Hot/Cold partitioning is not currently supported, since we can't handle literal pool placement in that case. */