From: Eddie Hung Date: Wed, 15 Jan 2020 22:42:00 +0000 (-0800) Subject: Update README.md for (* abc9_required *) X-Git-Tag: working-ls180~822^2~4 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=168c9d5871e331341058b026cf9b4f6a99a0f759;p=yosys.git Update README.md for (* abc9_required *) --- diff --git a/README.md b/README.md index 77e9410da..043e772ba 100644 --- a/README.md +++ b/README.md @@ -373,10 +373,15 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. -- The port attribute ``abc9_arrival`` specifies an integer (for output ports - only) to be used as the arrival time of this sequential port. It can be used, - for example, to specify the clk-to-Q delay of a flip-flop for consideration - during `abc9` techmapping. +- The output port attribute ``abc9_arrival`` specifies an integer, or a string + of space-separated integers to be used as the arrival time of this blackbox + port. It can be used, for example, to specify the clk-to-Q delay of a flip- + flop output for consideration during `abc9` techmapping. + +- The input port attribute ``abc9_requiredl`` specifies an integer, or a string + of space-separated integers to be used as the required time of this blackbox + port. It can be used, for example, to specify the setup-time of a flip-flop + input for consideration during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform