From: Pawel Sagan <psagan@internships.antmicro.com>
Date: Thu, 25 Jun 2020 12:32:50 +0000 (+0200)
Subject: i2s: Fix the incorrect TX fifo almost empty offset
X-Git-Tag: 24jan2021_ls180~117^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16a0aebcadf4a400ea4e430f6d74f7b791891110;p=litex.git

i2s: Fix the incorrect TX fifo almost empty offset
---

diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index 14ba8415..a5dde4ca 100644
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -495,7 +495,7 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                 p_DEVICE              = "7SERIES",
                 p_FIFO_SIZE           = "18Kb",
                 p_DATA_WIDTH          = fifo_data_width,
-                p_ALMOST_EMPTY_OFFSET = fifo_depth,
+                p_ALMOST_EMPTY_OFFSET = (512 - fifo_depth),
                 p_ALMOST_FULL_OFFSET  = 8,
                 p_DO_REG              = 0,
                 i_CLK         = ClockSignal(),