From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 15 Feb 2021 17:06:12 +0000 (-0300)
Subject: Simplify obtaining the PC from the register file
X-Git-Tag: convert-csv-opcode-to-binary~229^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16a332d4d943f6a973df75d8c1f85aef6eb0edf8;p=soc.git

Simplify obtaining the PC from the register file
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 98d42840..6f7c8ffd 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -173,7 +173,7 @@ def check_regs(dut, sim, core, test, code):
     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 
     # Check the PC as well
-    state = core.regs.rf['state']
+    state = core.regs.state
     pc = yield state.r_ports['cia'].data_o
     e_pc = sim.pc.CIA.value
     dut.assertEqual(e_pc, pc)