From: lkcl <lkcl@web>
Date: Wed, 9 Aug 2023 21:37:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16a7b1928ea75f564f168e5b8dad1849f98af66a;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn
index fd1ece72d..a848c4e4e 100644
--- a/3d_gpu/architecture/inorder_model.mdwn
+++ b/3d_gpu/architecture/inorder_model.mdwn
@@ -8,7 +8,7 @@ approximately 10-15 lines of python code to get it actually running a first unit
 
 The Libre-SOC TestIssuer core
 utilises a Finite-State Machine (FSM) to control the fetch/dec/issue/exec
-pipelines, with only one pipeline being active at any given time. This is good
+Computational Units, with only one such CompUnit (a FSM or a pipeline) being active at any given time. This is good
 for debugging the HDL, but severly restricts performance as a single
 instruction will take tens of clock cycles to complete.  In-development
 (Andrey to research and link to the relevant bugreport) is an in-order