From: Jason Ekstrand <jason@jlekstrand.net>
Date: Fri, 27 Mar 2020 16:49:14 +0000 (-0500)
Subject: aco: Implement b2b32 and b2b1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16a80ff18a0c6210f9c4c6d2668537dba2349608;p=mesa.git

aco: Implement b2b32 and b2b1

The implementations here just clone i2b32 and i2b1.  This means that
b2b32 doesn't technically generate true NIR 0/-1 booleans but it should
be fine as it's only ever generated for shared variable writes which
will always be consumed by something which will then run it through an
i2b again.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
---

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index fa3d38e1be7..8b8f3fa8ce0 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2247,6 +2247,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
       }
       break;
    }
+   case nir_op_b2b32:
    case nir_op_b2i32: {
       Temp src = get_alu_src(ctx, instr->src[0]);
       assert(src.regClass() == bld.lm);
@@ -2261,6 +2262,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
       }
       break;
    }
+   case nir_op_b2b1:
    case nir_op_i2b1: {
       Temp src = get_alu_src(ctx, instr->src[0]);
       assert(dst.regClass() == bld.lm);
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 644bc151fcb..d365f79698a 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -323,11 +323,13 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_op_ieq:
                   case nir_op_ine:
                   case nir_op_i2b1:
+                  case nir_op_b2b1:
                      size = lane_mask_size;
                      break;
                   case nir_op_f2i64:
                   case nir_op_f2u64:
                   case nir_op_b2i32:
+                  case nir_op_b2b32:
                   case nir_op_b2f32:
                   case nir_op_f2i32:
                   case nir_op_f2u32: