From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Jun 2020 06:14:49 +0000 (+0100)
Subject: add fast spr1/2 sim ALUHelpers
X-Git-Tag: div_pipeline~401
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16aad50eade507bbb48bdee5b50244f64ba3bb47;p=soc.git

add fast spr1/2 sim ALUHelpers
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index b7d5ec8a..c2eb0888 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -56,25 +56,9 @@ def get_cu_inputs(dec2, sim):
     # CIA (PC)
     res['cia'] = sim.pc.CIA.value
 
-    fast1_en = yield dec2.e.read_fast1.ok
-    if fast1_en:
-        fast1_sel = yield dec2.e.read_fast1.data
-        spr1_sel = fast_reg_to_spr(fast1_sel)
-        spr1_data = sim.spr[spr1_sel].value
-        res['spr1'] = spr1_data
-
-    fast2_en = yield dec2.e.read_fast2.ok
-    if fast2_en:
-        fast2_sel = yield dec2.e.read_fast2.data
-        spr2_sel = fast_reg_to_spr(fast2_sel)
-        spr2_data = sim.spr[spr2_sel].value
-        res['spr2'] = spr2_data
-
-    cr_en = yield dec2.e.read_cr1.ok
-    if cr_en:
-        cr_sel = yield dec2.e.read_cr1.data
-        cr = sim.crl[cr_sel].get_range().value
-        res['cr_a'] = cr
+    yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
+    yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
+    yield from ALUHelpers.get_sim_cr_a(res, sim, dec2)
 
     print ("get inputs", res)
     return res
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 2ca7df63..66d248b1 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -4,6 +4,7 @@ Bugreports:
 """
 
 from soc.decoder.power_enums import XER_bits
+from soc.regfile.util import fast_reg_to_spr # HACK!
 
 
 class TestCase:
@@ -27,6 +28,22 @@ class TestCase:
 
 class ALUHelpers:
 
+    def get_sim_fast_spr1(res, sim, dec2):
+        fast1_en = yield dec2.e.read_fast1.ok
+        if fast1_en:
+            fast1_sel = yield dec2.e.read_fast1.data
+            spr1_sel = fast_reg_to_spr(fast1_sel)
+            spr1_data = sim.spr[spr1_sel].value
+            res['spr1'] = spr1_data
+
+    def get_sim_fast_spr2(res, sim, dec2):
+        fast2_en = yield dec2.e.read_fast2.ok
+        if fast2_en:
+            fast2_sel = yield dec2.e.read_fast2.data
+            spr2_sel = fast_reg_to_spr(fast2_sel)
+            spr2_data = sim.spr[spr2_sel].value
+            res['spr2'] = spr2_data
+
     def get_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.read_cr1.ok
         if cridx_ok: