From: David S. Miller Date: Tue, 11 Aug 1998 23:50:23 +0000 (+0000) Subject: sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGE... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16cf811987ae3f713a00d42238cb76cc4326ad3a;p=gcc.git sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGET_ARCH64. * config/sparc/sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGET_ARCH64. (define_insn addx_extend_sp32 and split): Version that works when not TARGET_ARCH64. (define_insn subx_extend): Likewise. (define_split adddi3 and subdi3 with zero extension): Fixup and correct bugs when not TARGET_ARCH64. From-SVN: r21677 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 69c50c5d3b0..7e6b5d0ae87 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Tue Aug 11 22:42:01 1998 David S. Miller + + * config/sparc/sparc.md (define_insn addx_extend): Rename to + addx_extend_sp64, only allow when TARGET_ARCH64. + (define_insn addx_extend_sp32 and split): Version that works when + not TARGET_ARCH64. + (define_insn subx_extend): Likewise. + (define_split adddi3 and subdi3 with zero extension): Fixup and + correct bugs when not TARGET_ARCH64. + Tue Aug 11 16:04:34 1998 John Carr * except.c (set_exception_lang_code, set_exception_version_code): diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f5897e6ca57..2245b363e68 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -4444,12 +4444,34 @@ movtf_is_ok: [(set_attr "type" "unary") (set_attr "length" "1")]) -(define_insn "*addx_extend" +(define_insn "*addx_extend_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - "" + "! TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") + (match_operand:SI 2 "arith_operand" "")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "! TARGET_ARCH64 && reload_completed" + [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) + (set (match_dup 4) (const_int 0))] + "operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[1]);") + +(define_insn "*addx_extend_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "TARGET_ARCH64" "addx\\t%r1, %2, %0" [(set_attr "type" "unary") (set_attr "length" "1")]) @@ -4464,16 +4486,38 @@ movtf_is_ok: [(set_attr "type" "unary") (set_attr "length" "1")]) -(define_insn "*subx_extend" +(define_insn "*subx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - "" + "TARGET_ARCH64" "subx\\t%r1, %2, %0" [(set_attr "type" "unary") (set_attr "length" "1")]) +(define_insn "*subx_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "! TARGET_ARCH64 && reload_completed" + [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) + (set (match_dup 4) (const_int 0))] + "operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[0]);") + ;; This is only for splits at the moment. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4487,8 +4531,8 @@ movtf_is_ok: (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r"))) + (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" @@ -4501,14 +4545,17 @@ movtf_is_ok: (match_operand:DI 2 "register_operand" ""))) (clobber (reg:CC 100))] "! TARGET_ARCH64" - [(set (reg:CC_NOOV 100) - (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) - (const_int 0))) - (set (match_dup 0) + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) + (const_int 0))) + (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))]) + (set (match_dup 6) (plus:SI (plus:SI (match_dup 4) (const_int 0)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "operands[3] = gen_lowpart (SImode, operands[2]); - operands[4] = gen_highpart (SImode, operands[2]);") + operands[4] = gen_highpart (SImode, operands[2]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[0]);") (define_insn "*adddi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4672,14 +4719,17 @@ movtf_is_ok: (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) (clobber (reg:CC 100))] "! TARGET_ARCH64" - [(set (reg:CC_NOOV 100) - (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) - (const_int 0))) - (set (match_dup 0) - (plus:SI (plus:SI (match_dup 4) (const_int 0)) - (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) + (const_int 0))) + (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))]) + (set (match_dup 6) + (minus:SI (minus:SI (match_dup 4) (const_int 0)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "operands[3] = gen_lowpart (SImode, operands[1]); - operands[4] = gen_highpart (SImode, operands[1]);") + operands[4] = gen_highpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[0]);") (define_insn "*subdi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r")