From: Nick Clifton <nickc@redhat.com>
Date: Mon, 18 Apr 2005 12:17:51 +0000 (+0000)
Subject: (WMAC, WMADD): Move casts from the LHS of an assignment operator to the RHS.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16d55f147928d49892095d21ad04ac40b852546d;p=binutils-gdb.git

(WMAC, WMADD): Move casts from the LHS of an assignment operator to the RHS.
(WSLL, WSRA, WSRL, WUNPCKEH, WUNPACKEL): Use ULL suffix to indicate an
unsigned long long constant.
---

diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index f2ceaeceb08..7a680f3d386 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,10 @@
+2005-04-18  Nick Clifton  <nickc@redhat.com>
+
+	* iwmmxt.c (WMAC, WMADD): Move casts from the LHS of an assignment
+	operator to the RHS.
+	(WSLL, WSRA, WSRL, WUNPCKEH, WUNPACKEL): Use ULL suffix to
+	indicate an unsigned long long constant.
+
 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 
 	* configure: Regenerate.
diff --git a/sim/arm/iwmmxt.c b/sim/arm/iwmmxt.c
index 72444f6fdbd..2e285e4eb51 100644
--- a/sim/arm/iwmmxt.c
+++ b/sim/arm/iwmmxt.c
@@ -2114,7 +2114,7 @@ WMAC (ARMword instr)
 
 	  s = (signed long) a * (signed long) b;
 
-	  (signed long long) t += s;
+	  t = t + (ARMdword) s;
         }
       else
         {
@@ -2130,7 +2130,7 @@ WMAC (ARMword instr)
     wR [BITS (12, 15)] = 0;
 
   if (BIT (21))	/* Signed.  */
-    (signed long long) wR[BITS (12, 15)] += (signed long long) t;
+    wR[BITS (12, 15)] += t;
   else
     wR [BITS (12, 15)] += t;
 
@@ -2166,7 +2166,7 @@ WMADD (ARMword instr)
 	  b = wRHALF (BITS (0, 3), i * 2);
 	  b = EXTEND16 (b);
 
-	  (signed long) s1 = a * b;
+	  s1 = (ARMdword) (a * b);
 
 	  a = wRHALF (BITS (16, 19), i * 2 + 1);
 	  a = EXTEND16 (a);
@@ -2174,7 +2174,7 @@ WMADD (ARMword instr)
 	  b = wRHALF (BITS (0, 3), i * 2 + 1);
 	  b = EXTEND16 (b);
 
-	  (signed long) s2 = a * b;
+	  s2 = (ARMdword) (a * b);
         }
       else			/* Unsigned.  */
         {
@@ -2183,12 +2183,12 @@ WMADD (ARMword instr)
 	  a = wRHALF (BITS (16, 19), i * 2);
 	  b = wRHALF (BITS ( 0,  3), i * 2);
 
-	  (unsigned long) s1 = a * b;
+	  s1 = (ARMdword) (a * b);
 
 	  a = wRHALF (BITS (16, 19), i * 2 + 1);
 	  b = wRHALF (BITS ( 0,  3), i * 2 + 1);
 
-	  (signed long) s2 = a * b;
+	  s2 = (ARMdword) a * b;
         }
 
       r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0);
@@ -2837,7 +2837,7 @@ WSLL (ARMul_State * state, ARMword instr)
       if (shift > 63)
 	r = 0;
       else
-	r = ((wR[BITS (16, 19)] & 0xffffffffffffffff) << shift);
+	r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift);
 
       SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
       SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
@@ -2914,9 +2914,9 @@ WSRA (ARMul_State * state, ARMword instr)
       
     case Dqual:
       if (shift > 63)
-	r = (wR [BITS (16, 19)] & 0x8000000000000000) ? 0xffffffffffffffff : 0;
+	r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0;
       else
-	r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffff) >> shift);
+	r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift);
       SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
       SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
       break;
@@ -2985,7 +2985,7 @@ WSRL (ARMul_State * state, ARMword instr)
       if (shift > 63)
 	r = 0;
       else
-	r = (wR [BITS (16, 19)] & 0xffffffffffffffff) >> shift;
+	r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift;
 
       SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
       SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
@@ -3287,7 +3287,7 @@ WUNPCKEH (ARMul_State * state, ARMword instr)
       r = wRWORD (BITS (16, 19), 1);
 
       if (BIT (21) && NBIT32 (r))
-	r |= 0xffffffff00000000;
+	r |= 0xffffffff00000000ULL;
 
       SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
       SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
@@ -3354,7 +3354,7 @@ WUNPCKEL (ARMul_State * state, ARMword instr)
       r = wRWORD (BITS (16, 19), 0);
 
       if (BIT (21) && NBIT32 (r))
-	r |= 0xffffffff00000000;
+	r |= 0xffffffff00000000ULL;
 
       SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
       SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);