From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 14 Apr 2021 19:29:22 +0000 (+0000)
Subject: add an SRAM and wishbone to add test (makes it bigger)
X-Git-Tag: LS180_RC3~116
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16e003d52e2590d150541e8b388d92d5c0c6617a;p=soclayout.git

add an SRAM and wishbone to add test (makes it bigger)
also enable HFNS.  this to test cocotb-ghdl
---

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index 09799d3..f0b47be 100644
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -10,6 +10,8 @@ from nmigen.cli import verilog
 # for each:  $ python3 setup.py develop # optional: --user
 
 from c4m.nmigen.jtag.tap import TAP, IOType
+from nmigen_soc.wishbone.sram import SRAM
+from nmigen import Memory
 
 
 class ADD(Elaboratable):
@@ -29,6 +31,15 @@ class ADD(Elaboratable):
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
 
+        # create and connect wishbone
+        self.wb = self.jtag.add_wishbone(ircodes=[5, 6, 7], features={'err'},
+                                   address_width=30, data_width=32,
+                                   granularity=8, # 8-bit wide
+                                   name="jtag_wb")
+
+        # create DMI2JTAG (goes through to dmi_sim())
+        self.dmi = self.jtag.add_dmi(ircodes=[8, 9, 10])
+
         # add iotypes
         self.io_a_0 = self.jtag.add_io(name="a_0", iotype=IOType.In)
         self.io_a_1 = self.jtag.add_io(name="a_1", iotype=IOType.In)
@@ -82,6 +93,21 @@ class ADD(Elaboratable):
         m.d.comb += self.io_f_2.core.o.eq(f[2])
         m.d.comb += self.io_f_3.core.o.eq(f[3])
 
+        # create a Memory
+        memory = Memory(width=32, depth=32)
+        sram   = SRAM(memory=memory, granularity=8)
+
+        m.submodules.sram   = sram
+
+        m.d.comb += sram.bus.cyc.eq(self.wb.cyc)
+        m.d.comb += sram.bus.stb.eq(self.wb.stb)
+        m.d.comb += sram.bus.we.eq(self.wb.we)
+        m.d.comb += sram.bus.sel.eq(self.wb.sel)
+        m.d.comb += sram.bus.adr.eq(self.wb.adr)
+        m.d.comb += sram.bus.dat_w.eq(self.wb.dat_w)
+
+        m.d.comb += self.wb.ack.eq(sram.bus.ack)
+        m.d.comb += self.wb.dat_r.eq(sram.bus.dat_r)
 
         # do a simple "add"
         m.d.sync += f.eq(a + b)
diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index a652193..33a2ed9 100644
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -27,6 +27,7 @@ def scriptMain ( **kw ):
     global af
     rvalue = True
     try:
+        coreSize = 10000
         helpers.setTraceLevel( 550 )
         cell, editor = plugins.kwParseMain( **kw )
         cell = af.getCell( 'add', CRL.Catalog.State.Logical )
@@ -72,13 +73,16 @@ def scriptMain ( **kw ):
         adderConf.editor = editor
         adderConf.useSpares = True
         adderConf.useClockTree = True
+        adderConf.useHFNS = True
+        adderConf.cfg.katana.hTracksReservedMin = 9
+        adderConf.cfg.katana.vTracksReservedMin = 2
         adderConf.bColumns = 2
         adderConf.bRows = 2
         adderConf.chipConf.name = 'chip'
         #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
         adderConf.chipConf.ioPadGauge = 'niolib'
-        adderConf.coreSize = ( l(2000), l(2000) )
-        adderConf.chipSize = ( l(5900), l(5900) )
+        adderConf.coreSize = ( l(coreSize), l(coreSize) )
+        adderConf.chipSize = ( l(coreSize+3500), l(coreSize+3500) )
         adderToChip = CoreToChip( adderConf )
         adderToChip.buildChip()