From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 15 Nov 2010 20:04:03 +0000 (-0600)
Subject: CPU: Fix bug when a split transaction is issued to a faster cache
X-Git-Tag: stable_2012_02_02~750
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16f210da3715bb69bed9a80a5cf0eeffec0edf7c;p=gem5.git

CPU: Fix bug when a split transaction is issued to a faster cache

In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
---

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2abe9cd59..7307f2fc9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -999,7 +999,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
         if (next_tick == curTick) {
             cpu->completeDataAccess(pkt);
         } else {
-            tickEvent.schedule(pkt, next_tick);
+            if (!tickEvent.scheduled()) {
+                tickEvent.schedule(pkt, next_tick);
+            } else {
+                // In the case of a split transaction and a cache that is
+                // faster than a CPU we could get two responses before
+                // next_tick expires
+                if (!retryEvent.scheduled())
+                    schedule(retryEvent, next_tick);
+                return false;
+            }
         }
 
         return true;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 65cbe3098..2b0c8942a 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -140,7 +140,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
-            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
+            : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
         { }
 
         bool snoopRangeSent;
@@ -161,12 +161,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
         {
             PacketPtr pkt;
             TimingSimpleCPU *cpu;
+            CpuPort *port;
 
             TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
             const char *description() const { return "Timing CPU tick"; }
             void schedule(PacketPtr _pkt, Tick t);
         };
 
+        EventWrapper<Port, &Port::sendRetry> retryEvent;
     };
 
     class IcachePort : public CpuPort