From: lkcl <lkcl@web>
Date: Thu, 6 Apr 2023 02:24:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16f87ef2d2d914b4fec9b24492ec823c9c2a088d;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e4ecb0652..7f8783dbc 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -442,18 +442,6 @@ would become a whopping 96-bit long instruction. Avoiding this
 situation is a high priority which in turn by necessity puts pressure
 on the 32-bit Major Opcode space.
 
-SVP64 itself is already under pressure, being only 24 bits.  If it is
-not permitted to take up 25% of EXT001 then it would have to be proposed
-in its own Major Opcode, which on first consideration would be beneficial
-for SVP64 due to the availability of 2 extra bits.
-However when combined with the bitmanip scalar instructions
-requiring two Major opcodes this would come to a grand total of 3 precious
-Major opcodes. On balance, then, sacrificing 25% of EXT001 is the "least
-difficult" choice.
-Alternative locations for SVP64
-Prefixing include EXT006 and EXT017, with EXT006 being most favourable
-as there is room for future expansion.
-
 Note also that EXT022, the Official Architectural Sandbox area
 available for "Custom non-approved purposes" according to the Power
 ISA Spec,