From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 24 Mar 2020 10:59:18 +0000 (+0000)
Subject: whitespace
X-Git-Tag: div_pipeline~1637
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16f8c5cd81e82c5da641a5fde1ad087218a62fb6;p=soc.git

whitespace
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 813dd19c..f7cd669c 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -88,7 +88,7 @@ class InternalOpSimulator:
         elif internal_op == InternalOp.OP_OR.value:
             return op1 | op2
         else:
-            assert False, "Not implemented" 
+            assert False, "Not implemented"
 
     def alu_op(self, pdecode2):
         internal_op = yield pdecode2.dec.op.internal_op
@@ -121,7 +121,7 @@ class InternalOpSimulator:
         internal_op = yield pdecode2.dec.op.internal_op
         addr_reg = yield pdecode2.e.read_reg1.data
         addr = self.regfile.read_reg(addr_reg)
-        
+ 
         imm_ok = yield pdecode2.e.imm_data.ok
         r2_ok = yield pdecode2.e.read_reg2.ok
         width = yield pdecode2.e.data_len
@@ -140,7 +140,6 @@ class InternalOpSimulator:
             val = self.mem_sim.ld(addr, width)
             self.regfile.write_reg(dest_reg, val)
 
-
     def execute_op(self, pdecode2):
         function = yield pdecode2.dec.op.function_unit
         if function == Function.ALU.value: