From: lkcl Date: Sat, 19 Dec 2020 18:23:18 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1177 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=16fb5667873d834694799afff28ec977846ad73d;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index e88b05079..f631fe6e3 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -439,6 +439,7 @@ CR element*. Greatly simplified pseudocode: CRs[8+i].gt = iregs[RT+i] > 0 ... +If a "cumulated" CR based analysis of results is desired, then a followup instruction must be performed, setting "reduce" mode on the Vector of CRs, using cr ops to do so. This provides far more flexibility in analysing vectors than standard Vector ISAs. Normal Vector ISAs are typically restricted to "were all results nonzero" and "were some results nonzero". The application of mapreduce to Vectorised cr operations allows far more sophisticated analysis. (see [[discussion]]. some alternative schemes are described there)