From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 25 Dec 2014 15:41:20 +0000 (+0100)
Subject: Fixed simplemap for $ne cells with output width > 1
X-Git-Tag: yosys-0.5~224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=170788a3decdf8b475762106df24eae910cf24c7;p=yosys.git

Fixed simplemap for $ne cells with output width > 1
---

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 694ebf226..9cea5f45d 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -241,18 +241,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
-
-	RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
-	RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
-
-	if (!is_ne)
-		module->addNotGate(NEW_ID, reduce_out, sig_y);
-
 	simplemap_bitop(module, xor_cell);
 	module->remove(xor_cell);
 
+	RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
+	RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
 	simplemap_reduce(module, reduce_cell);
 	module->remove(reduce_cell);
+
+	if (!is_ne) {
+		RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
+		simplemap_lognot(module, not_cell);
+		module->remove(not_cell);
+	}
 }
 
 void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)