From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 17:31:02 +0000 (+0100)
Subject: missing test.mem arg for ISA in test_core
X-Git-Tag: div_pipeline~526
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=172eee700ecddedbf9d66883d9cbb20cb13f0646;p=soc.git

missing test.mem arg for ISA in test_core
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index ace4b256..17742940 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -77,7 +77,7 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))