From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 9 Mar 2019 03:51:52 +0000 (-0800)
Subject: Add comments for VectorAssembler
X-Git-Tag: div_pipeline~2332
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17386714cca7f382c1c427ce4fdc14418f7e9c77;p=soc.git

Add comments for VectorAssembler
---

diff --git a/TLB/src/VectorAssembler.py b/TLB/src/VectorAssembler.py
index 517dc51e..a0b0e859 100644
--- a/TLB/src/VectorAssembler.py
+++ b/TLB/src/VectorAssembler.py
@@ -2,7 +2,19 @@ from nmigen import Array, Module, Signal
 from nmigen.cli import main 
 
 class VectorAssembler():
+    """ Vector Assembler
+    
+        The purpose of this module is to take a generic number of inputs
+        and cleanly combine them into one vector. While this is very much 
+        possible through raw code it may result in a very unfortunate sight
+        in a yosys graph. Thus this class was born! No more will ugly loops 
+        exist in my graphs! Get outta here ya goddam Lochness Monster. 
+    """
     def __init__(self, width):
+        """ Arguments:
+            * width: (bit count) The desiered size of the output vector
+        
+        """
         # Internal
         self.width = width
         
diff --git a/TLB/test/test_vector_assembler.py b/TLB/test/test_vector_assembler.py
index 8e07c9c7..49d48c47 100644
--- a/TLB/test/test_vector_assembler.py
+++ b/TLB/test/test_vector_assembler.py
@@ -7,21 +7,36 @@ from nmigen.compat.sim import run_simulation
 from test_helper import assert_eq, assert_ne, assert_op
 from VectorAssembler import VectorAssembler
 
+# Constant that defines size of output 
+# Dont change this unless you change the input vectors to match!
 assembler_size = 4
 
+# This function allows for the easy setting of values to the VectorAssembler
+# Arguments:
+#   dut: The CamEntry being tested
+#   input: The array of single bits to be written
 def set_assembler(dut, input):
     assert len(input) == assembler_size
     for index in range(assembler_size):
+        # Make sure we start from the beginning of the array
+        # at least the side that makes sense from a human standpoint
+        # of reading bits
         input_index = assembler_size - index - 1
         yield dut.input[index].eq(input[input_index])
     yield
     
+# Checks the data state of the CAM entry
+# Arguments:
+#   dut: The CamEntry being tested
+#   o (Output): The expected output
+#   op (Operation): (0 => ==), (1 => !=)
 def check_output(dut, o, op):
     out_o = yield dut.o
     assert_op("Output", out_o, o, op)
     
-
 def testbench(dut):
+    # Input should but bit readable from left to right
+    # with Little Endian notation
     input = [1, 1, 0, 0]
     output = 12
     yield from set_assembler(dut, input)