From: David Shah <dave@ds0.me>
Date: Fri, 20 Sep 2019 12:01:47 +0000 (+0100)
Subject: Update CHANGELOG and README
X-Git-Tag: working-ls180~995^2^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1746b6373b55490314bc2e12c6584c4a1cb38a6a;p=yosys.git

Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/CHANGELOG b/CHANGELOG
index c1ffaa44a..51d5e1dc9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
+    - Added support for SystemVerilog typedefs
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------
diff --git a/README.md b/README.md
index fdd4bb410..db7810cb4 100644
--- a/README.md
+++ b/README.md
@@ -510,6 +510,8 @@ from SystemVerilog:
   into a design with ``read_verilog``, all its packages are available to
   SystemVerilog files being read into the same design afterwards.
 
+- typedefs are supported (including inside packages)
+
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.