From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 26 Feb 2020 16:46:23 +0000 (-0500)
Subject: Rename bitrev signal to shift_right (more descriptive)
X-Git-Tag: ls180-24jan2020~118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1754d05f279091f4fe05d66c08a748f744b2f755;p=ieee754fpu.git

Rename bitrev signal to shift_right (more descriptive)
---

diff --git a/src/ieee754/part_shift/formal/proof_shift_dynamic.py b/src/ieee754/part_shift/formal/proof_shift_dynamic.py
index 1c9bc478..9c160762 100644
--- a/src/ieee754/part_shift/formal/proof_shift_dynamic.py
+++ b/src/ieee754/part_shift/formal/proof_shift_dynamic.py
@@ -38,7 +38,7 @@ class ShifterDriver(Elaboratable):
         # setup the inputs and outputs of the DUT as anyconst
         a = Signal(width)
         b = Signal(width)
-        bitrev = Signal()
+        shift_right = Signal()
         out = Signal(width)
         points = PartitionPoints()
         gates = Signal(mwidth-1)
@@ -49,7 +49,7 @@ class ShifterDriver(Elaboratable):
 
         comb += [a.eq(AnyConst(width)),
                  b.eq(AnyConst(width)),
-                 bitrev.eq(AnyConst(1)),
+                 shift_right.eq(AnyConst(1)),
                  gates.eq(AnyConst(mwidth-1))]
 
         m.submodules.dut = dut = PartitionedDynamicShift(width, points)
@@ -60,11 +60,11 @@ class ShifterDriver(Elaboratable):
 
         comb += [dut.a.eq(a),
                  dut.b.eq(b),
-                 dut.bitrev.eq(bitrev),
+                 dut.shift_right.eq(shift_right),
                  out.eq(dut.output)]
 
 
-        with m.If(bitrev == 0):
+        with m.If(shift_right == 0):
             with m.Switch(points.as_sig()):
                 with m.Case(0b000):
                     comb += Assert(out == (a<<b[0:5]) & 0xffffffff)
diff --git a/src/ieee754/part_shift/formal/proof_shift_scalar.py b/src/ieee754/part_shift/formal/proof_shift_scalar.py
index 35dd993e..7c0d7593 100644
--- a/src/ieee754/part_shift/formal/proof_shift_scalar.py
+++ b/src/ieee754/part_shift/formal/proof_shift_scalar.py
@@ -41,14 +41,14 @@ class ShifterDriver(Elaboratable):
         shifter = Signal(shifterwidth)
         points = PartitionPoints()
         gates = Signal(mwidth-1)
-        bitrev = Signal()
+        shift_right = Signal()
         step = int(width/mwidth)
         for i in range(mwidth-1):
             points[(i+1)*step] = gates[i]
         print(points)
 
         comb += [data.eq(AnyConst(width)),
-                 bitrev.eq(AnyConst(1)),
+                 shift_right.eq(AnyConst(1)),
                  shifter.eq(AnyConst(shifterwidth)),
                  gates.eq(AnyConst(mwidth-1))]
 
@@ -59,12 +59,12 @@ class ShifterDriver(Elaboratable):
 
         comb += [dut.data.eq(data),
                  dut.shifter.eq(shifter),
-                 dut.bitrev.eq(bitrev),
+                 dut.shift_right.eq(shift_right),
                  out.eq(dut.output)]
 
         expected = Signal(width)
 
-        with m.If(bitrev == 0):
+        with m.If(shift_right == 0):
             with m.Switch(points.as_sig()):
                 with m.Case(0b00):
                     comb += Assert(
diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 15ecd3bc..ba653fcf 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -104,7 +104,7 @@ class PartitionedDynamicShift(Elaboratable):
 
         self.a = Signal(width, reset_less=True)
         self.b = Signal(width, reset_less=True)
-        self.bitrev = Signal(reset_less=True)
+        self.shift_right = Signal(reset_less=True)
         self.output = Signal(width, reset_less=True)
 
     def elaborate(self, platform):
@@ -121,15 +121,15 @@ class PartitionedDynamicShift(Elaboratable):
 
         m.submodules.a_br = a_br = GatedBitReverse(self.a.width)
         comb += a_br.data.eq(self.a)
-        comb += a_br.reverse_en.eq(self.bitrev)
+        comb += a_br.reverse_en.eq(self.shift_right)
 
         m.submodules.out_br = out_br = GatedBitReverse(self.output.width)
-        comb += out_br.reverse_en.eq(self.bitrev)
+        comb += out_br.reverse_en.eq(self.shift_right)
         comb += self.output.eq(out_br.output)
 
         m.submodules.gate_br = gate_br = GatedBitReverse(pwid)
         comb += gate_br.data.eq(gates)
-        comb += gate_br.reverse_en.eq(self.bitrev)
+        comb += gate_br.reverse_en.eq(self.shift_right)
 
 
         # break out both the input and output into partition-stratified blocks
@@ -205,7 +205,7 @@ class PartitionedDynamicShift(Elaboratable):
         for i in range(len(b_shl_amount)):
             shift_amount = Signal(masked_b[i].width, name="shift_amount%d" % i)
             comb += shift_amount.eq(
-                Mux(self.bitrev, b_shr_amount[i], b_shl_amount[i]))
+                Mux(self.shift_right, b_shr_amount[i], b_shl_amount[i]))
             shift_amounts.append(shift_amount)
 
         partial_results = []
diff --git a/src/ieee754/part_shift/part_shift_scalar.py b/src/ieee754/part_shift/part_shift_scalar.py
index 79fc3e69..7cc8ff5b 100644
--- a/src/ieee754/part_shift/part_shift_scalar.py
+++ b/src/ieee754/part_shift/part_shift_scalar.py
@@ -28,8 +28,7 @@ class PartitionedScalarShift(Elaboratable):
         self.shiftbits = math.ceil(math.log2(width))
         self.shifter = Signal(self.shiftbits, reset_less=True)
         self.output = Signal(width, reset_less=True)
-        self.bitrev = Signal(reset_less=True) # Whether to bit-reverse the
-                                              # input and output
+        self.shift_right = Signal(reset_less=True) # Whether to shift right
 
     def elaborate(self, platform):
         m = Module()
@@ -47,15 +46,15 @@ class PartitionedScalarShift(Elaboratable):
 
         m.submodules.in_br = in_br = GatedBitReverse(self.data.width)
         comb += in_br.data.eq(self.data)
-        comb += in_br.reverse_en.eq(self.bitrev)
+        comb += in_br.reverse_en.eq(self.shift_right)
 
         m.submodules.out_br = out_br = GatedBitReverse(self.data.width)
-        comb += out_br.reverse_en.eq(self.bitrev)
+        comb += out_br.reverse_en.eq(self.shift_right)
         comb += self.output.eq(out_br.output)
 
         m.submodules.gate_br = gate_br = GatedBitReverse(pwid)
         comb += gate_br.data.eq(gates)
-        comb += gate_br.reverse_en.eq(self.bitrev)
+        comb += gate_br.reverse_en.eq(self.shift_right)
         start = 0
         for i in range(len(keys)):
             end = keys[i]