From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 16 Jan 2015 19:53:17 +0000 (+0100)
Subject: use csr_data_width of 32 to speed up data mila upload
X-Git-Tag: 24jan2021_ls180~2572^2~54
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=175618bcb4f9a3a8110022f4df7f956b447af7bd;p=litex.git

use csr_data_width of 32 to speed up data mila upload
---

diff --git a/lib/sata/phy/__init__.py b/lib/sata/phy/__init__.py
index 98afb13c..925d7720 100644
--- a/lib/sata/phy/__init__.py
+++ b/lib/sata/phy/__init__.py
@@ -1,5 +1,5 @@
 from lib.sata.common import *
-from lib.sata.phy.ctrl import SATAPHYHostCtrl, SATAPHYDeviceCtrl
+from lib.sata.phy.ctrl import SATAPHYHostCtrl
 from lib.sata.phy.datapath import SATAPHYDatapath
 
 class SATAPHY(Module):
diff --git a/targets/bist.py b/targets/bist.py
index 0e101543..e1b562fd 100644
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -54,7 +54,7 @@ class _CRG(Module):
 
 class GenSoC(Module):
 	csr_base = 0x00000000
-	csr_data_width = 8
+	csr_data_width = 32
 	csr_map = {
 		"uart2wb":			0,
 		"identifier":		2,
diff --git a/test/config.py b/test/config.py
index c27ac821..5b274b23 100644
--- a/test/config.py
+++ b/test/config.py
@@ -1,7 +1,7 @@
 from miscope.host.uart2wishbone import Uart2Wishbone
 
 csr_csv_file = "./csr.csv"
-busword = 8
+busword = 32
 debug_wb = False
 
 com = 2