From: lkcl <lkcl@web>
Date: Wed, 14 Jul 2021 13:58:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~619
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17636b1e066348a8afb8b07f662c3a9d18ea1b8f;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/decoder.mdwn b/3d_gpu/architecture/decoder.mdwn
index 6fc827030..c720b9848 100644
--- a/3d_gpu/architecture/decoder.mdwn
+++ b/3d_gpu/architecture/decoder.mdwn
@@ -1,8 +1,9 @@
 # Decoder
 
-<http://bugs.libre-riscv.org/show_bug.cgi?id=186>
+* Context and walkthrough <https://libre-soc.org/irclog/%23libre-soc.2021-07-13.log.html>
+* bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=186>
 
-The decoder is in charge of translating the POWER instruction stream into operations that can be handled by our backend. It will have an extra input bit, set via a MSR, that will switch on GPU instructions.
+The decoder is in charge of translating the POWER instruction stream into operations that can be handled by the backend.
 
 Source code: <https://git.libre-riscv.org/?p=soc.git;a=tree;f=src/soc/decoder;hb=HEAD>