From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 00:29:23 +0000 (+0000)
Subject: add sub-calling of ports on o_data/i_data in ControlBase.ports
X-Git-Tag: ls180-24jan2020~1450
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17667d146448323213ed756100b3609a08e3db31;p=ieee754fpu.git

add sub-calling of ports on o_data/i_data in ControlBase.ports
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 4b61c4c5..493fa553 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -385,7 +385,7 @@ class ControlBase:
             * p: contains ready/valid to the previous stage
             * n: contains ready/valid to the next stage
 
-            User must also:
+            Except when calling Controlbase.connect(), user must also:
             * add i_data member to PrevControl (p) and
             * add o_data member to NextControl (n)
         """
@@ -468,10 +468,18 @@ class ControlBase:
         return eq(self.p.i_data, i)
 
     def ports(self):
-        return [self.p.i_valid, self.n.i_ready,
+        res = [self.p.i_valid, self.n.i_ready,
                 self.n.o_valid, self.p.o_ready,
-                self.p.i_data, self.n.o_data   # XXX need flattening!
                ]
+        if hasattr(self.p.i_data, "ports"):
+            res += self.p.i_data.ports()
+        else:
+            res += self.p.i_data
+        if hasattr(self.n.o_data, "ports"):
+            res += self.n.o_data.ports()
+        else:
+            res += self.n.o_data
+        return res
 
 
 class BufferedPipeline(ControlBase):