From: enjoy-digital Date: Thu, 10 Oct 2019 17:31:09 +0000 (+0200) Subject: Merge pull request #277 from railnova/feature/vivado_sysverilog_support X-Git-Tag: 24jan2021_ls180~928 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17756f631bd5cd72f3b8bb577bdbb05598179d8b;p=litex.git Merge pull request #277 from railnova/feature/vivado_sysverilog_support [feature] Add SystemVerilog support for the Vivado builder --- 17756f631bd5cd72f3b8bb577bdbb05598179d8b