From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Apr 2021 17:34:30 +0000 (+0000)
Subject: add two SRAMs, document how to do more
X-Git-Tag: LS180_RC3~99
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=177668f4e940511fb73b045fb86963e2ebbbf451;p=soclayout.git

add two SRAMs, document how to do more
---

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index f0b47be..fa7c2f0 100644
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -31,11 +31,31 @@ class ADD(Elaboratable):
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
 
-        # create and connect wishbone
-        self.wb = self.jtag.add_wishbone(ircodes=[5, 6, 7], features={'err'},
-                                   address_width=30, data_width=32,
+        # decide how many SRAMs you want to create (and what sizes)
+        # simply edit this before running "make lvx"
+        # try not to go above 3 because you run out of JTAG ircodes that way.
+        # if you really really must, then increase ir_width above, first
+        self.memsizes = []
+        #self.memsizes.append((32, 32)) # width, depth
+        self.memsizes.append((32, 16)) # width, depth
+        self.memsizes.append((32, 16)) # width, depth
+
+        # create and connect wishbone(s).  okok, a better solution is to
+        # use a Wishbone Arbiter, and only have one WB bus.
+        self.wb = []
+        ircode = 5 # start at 5,6,7 then jump 11,12,13 then 14,15,16 etc. etc.
+        for i, (width, depth) in enumerate(self.memsizes):
+            ircodes = [ircode, ircode+1, ircode+2]
+            if ircode == 5:
+                # next one skips DMI (see below - 8,9,10 already used)
+                ircode = 11
+            else:
+                ircode += 3
+            wb = self.jtag.add_wishbone(ircodes=ircodes, features={'err'},
+                                   address_width=30, data_width=width,
                                    granularity=8, # 8-bit wide
-                                   name="jtag_wb")
+                                   name="jtag_wb_%d" % i)
+            self.wb.append(wb)
 
         # create DMI2JTAG (goes through to dmi_sim())
         self.dmi = self.jtag.add_dmi(ircodes=[8, 9, 10])
@@ -93,21 +113,22 @@ class ADD(Elaboratable):
         m.d.comb += self.io_f_2.core.o.eq(f[2])
         m.d.comb += self.io_f_3.core.o.eq(f[3])
 
-        # create a Memory
-        memory = Memory(width=32, depth=32)
-        sram   = SRAM(memory=memory, granularity=8)
-
-        m.submodules.sram   = sram
-
-        m.d.comb += sram.bus.cyc.eq(self.wb.cyc)
-        m.d.comb += sram.bus.stb.eq(self.wb.stb)
-        m.d.comb += sram.bus.we.eq(self.wb.we)
-        m.d.comb += sram.bus.sel.eq(self.wb.sel)
-        m.d.comb += sram.bus.adr.eq(self.wb.adr)
-        m.d.comb += sram.bus.dat_w.eq(self.wb.dat_w)
-
-        m.d.comb += self.wb.ack.eq(sram.bus.ack)
-        m.d.comb += self.wb.dat_r.eq(sram.bus.dat_r)
+        # create Memories, each with their own individual JTAG bus
+        for i, (width, depth) in enumerate(self.memsizes):
+            memory = Memory(width=width, depth=depth)
+            sram   = SRAM(memory=memory, granularity=8)
+            m.submodules['sram%d' % i] = sram
+            wb = self.wb[i]
+
+            m.d.comb += sram.bus.cyc.eq(wb.cyc)
+            m.d.comb += sram.bus.stb.eq(wb.stb)
+            m.d.comb += sram.bus.we.eq(wb.we)
+            m.d.comb += sram.bus.sel.eq(wb.sel)
+            m.d.comb += sram.bus.adr.eq(wb.adr)
+            m.d.comb += sram.bus.dat_w.eq(wb.dat_w)
+
+            m.d.comb += wb.ack.eq(sram.bus.ack)
+            m.d.comb += wb.dat_r.eq(sram.bus.dat_r)
 
         # do a simple "add"
         m.d.sync += f.eq(a + b)