From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 13:30:01 +0000 (+0100) Subject: use nmutil exts helper X-Git-Tag: div_pipeline~1046 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=178b6c9f8a14d6ee4364859a55d1e23c0f0668c8;p=soc.git use nmutil exts helper --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 862c5ea3..3b9beba9 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -7,6 +7,7 @@ from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record from nmigen.cli import rtlil from nmutil.iocontrol import RecordObject +from nmutil.extend import exts from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_enums import (InternalOp, CryIn, Function, @@ -94,13 +95,6 @@ class DecodeB(Elaboratable): self.imm_out = Data(64, "imm_b") self.spr_out = Data(10, "spr_b") - def exts(self, exts_data, width, fullwidth): - exts_data = exts_data[0:width] - topbit = exts_data[-1] - signbits = Repl(topbit, fullwidth-width) - return Cat(exts_data, signbits) - - def elaborate(self, platform): m = Module() comb = m.d.comb @@ -115,7 +109,7 @@ class DecodeB(Elaboratable): comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here? comb += self.imm_out.data.eq( - self.exts(self.dec.SI, 16, 64)) + exts(self.dec.SI, 16, 64)) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_UI_HI): comb += self.imm_out.data.eq(self.dec.UI<<16) @@ -123,7 +117,7 @@ class DecodeB(Elaboratable): with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here? comb += self.imm_out.data.eq(self.dec.SI<<16) comb += self.imm_out.data.eq( - self.exts(self.dec.SI << 16, 32, 64)) + exts(self.dec.SI << 16, 32, 64)) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_LI): comb += self.imm_out.data.eq(self.dec.LI<<2)