From: umarcor <unai.martinezcorral@ehu.eus>
Date: Wed, 21 Jul 2021 17:54:27 +0000 (+0200)
Subject: VUnit: style
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=178c2a7da31b5939b34030d3fd7ba12e0563fbf1;p=microwatt.git

VUnit: style

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
---

diff --git a/run.py b/run.py
index a01c11d..3bf49da 100644
--- a/run.py
+++ b/run.py
@@ -1,28 +1,23 @@
 from pathlib import Path
 from vunit import VUnit
 
-prj = VUnit.from_argv()
-prj.add_osvvm()
-root = Path(__file__).parent
+ROOT = Path(__file__).parent
 
-lib = prj.add_library("lib")
-lib.add_source_files(root / "litedram" / "extras" / "*.vhdl")
-lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")
+PRJ = VUnit.from_argv()
+PRJ.add_osvvm()
 
-# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
-vhdl_files = root.glob("*.vhdl")
-vhdl_files = [
+PRJ.add_library("lib").add_source_files([
+    ROOT / "litedram" / "extras" / "*.vhdl",
+    ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
+] + [
     src_file
-    for src_file in vhdl_files
-    if ("xilinx-mult" not in src_file)
-    and ("foreign_random" not in src_file)
-    and ("nonrandom" not in src_file)
-]
-lib.add_source_files(vhdl_files)
+    for src_file in ROOT.glob("*.vhdl")
+    # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
+    if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
+])
 
-unisim = prj.add_library("unisim")
-unisim.add_source_files(root / "sim-unisim" / "*.vhdl")
+PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
 
-prj.set_sim_option("disable_ieee_warnings", True)
+PRJ.set_sim_option("disable_ieee_warnings", True)
 
-prj.main()
+PRJ.main()