From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 18 Aug 2009 03:25:14 +0000 (-0700)
Subject: X86: Implement LDMXCSR.
X-Git-Tag: Calvin_Submission~54
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=179fd4e536e12cbd1baeefbd9d8ac0557f899003;p=gem5.git

X86: Implement LDMXCSR.
---

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 5d817d2c2..dabc1bb75 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -828,7 +828,7 @@
                 0x6: decode MODRM_REG {
                     0x0: fxsave();
                     0x1: fxrstor();
-                    0x2: ldmxcsr();
+                    0x2: Inst::LDMXCSR(Md);
                     0x3: Inst::STMXCSR(Md);
                     0x4: Inst::UD2();
                     0x5: decode MODRM_MOD {
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 831a266c7..2481b744f 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -64,5 +64,15 @@ def macroop STMXCSR_P {
     rdip t7
     st t1, seg, riprel, disp
 };
-# LDMXCSR
+
+def macroop LDMXCSR_M {
+    ld t1, seg, sib, disp
+    wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
+
+def macroop LDMXCSR_P {
+    rdip t7
+    ld t1, seg, riprel, disp
+    wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
 '''