From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 16 Jun 2021 19:29:54 +0000 (+0100)
Subject: sorted out order of FPMULADD32 helper, only have rounding errors now
X-Git-Tag: xlen-bcd~438
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17ab6614b27c898c570631ed286c9b37759c5167;p=openpower-isa.git

sorted out order of FPMULADD32 helper, only have rounding errors now
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index 134ef84a..3549516a 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -289,7 +289,7 @@ def FPMUL32(FRA, FRB):
     return cvt
 
 
-def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
+def FPMULADD32(FRA, FRC, FRB, mulsign, addsign):
     from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
     #return FPMUL64(FRA, FRB)
     #FRA = DOUBLE(SINGLE(FRA))
@@ -298,12 +298,12 @@ def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
         if mulsign == 1:
             result = float(FRA) * float(FRC) + float(FRB) # fmadds
         elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
+            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
     elif addsign == -1:
         if mulsign == 1:
             result = float(FRA) * float(FRC) - float(FRB) # fmsubs
         elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
+            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
     elif addsign == 0:
         result = 0.0
     log ("FPMULADD32", FRA, FRB, FRC,