From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 Sep 2021 16:13:45 +0000 (+0100)
Subject: reduce part_mask in partsig tests to 3 (actual number of break points
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17afe2df630b8075907c13529d46ad124c980954;p=ieee754fpu.git

reduce part_mask in partsig tests to 3 (actual number of break points
not actual number of partitions), fix PartitionedSignal.like(),
needed to pass in PartitionPoints(other.partpoints)
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index b5faf35a..6baca3ad 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -80,7 +80,7 @@ class PartitionedSignal(UserValue):
     def like(other, *args, **kwargs):
         """Builds a new PartitionedSignal with the same PartitionPoints and
         Signal properties as the other"""
-        result = PartitionedSignal(other.partpoints)
+        result = PartitionedSignal(PartitionPoints(other.partpoints))
         result.sig = Signal.like(other.sig, *args, **kwargs)
         result.m = other.m
         return result
diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 387a2e9c..39bd5f5f 100644
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -222,7 +222,7 @@ class TestAddMod(Elaboratable):
 class TestMux(unittest.TestCase):
     def test(self):
         width = 16
-        part_mask = Signal(4)  # divide into 4-bits
+        part_mask = Signal(3)  # divide into 4-bits
         module = TestMuxMod(width, part_mask)
 
         test_name = "part_sig_mux"
@@ -407,7 +407,7 @@ class TestCat(unittest.TestCase):
 class TestPartitionedSignal(unittest.TestCase):
     def test(self):
         width = 16
-        part_mask = Signal(4)  # divide into 4-bits
+        part_mask = Signal(3)  # divide into 4-bits
         module = TestAddMod(width, part_mask)
 
         test_name = "part_sig_add"