From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 28 Sep 2022 13:34:21 +0000 (+0100)
Subject: comments on horizontal-or
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17c8464c3fd36da91ce88ed86acda7e65f0aff02;p=openpower-isa.git

comments on horizontal-or
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index a2b97174..e77877de 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -192,9 +192,13 @@ class DecoderTestCase(FHDLTestCase):
                         "svremap 31, 1, 3, 1, 1, 1, 0",
                         "sv.or *0, *0, *6"
                         ]
-                REMAP horizontal-or on RA,RS,RB
+                REMAP horizontal-or using "or RA,RS,RB"
+                same trick can be applied to do horizontal-add
+                or horizontal-multiply.  just remember for multiply
+                to pre-load 1 (1.0) into the results first (or any other
+                scaling factor).
 
-                This is horribly obscure because RA (the destination)
+                sv.or is horribly obscure because RA (the destination)
                 actually gets treated as RT by the REMAP subsystem.
 
                 The purpose here is to demonstrate a horizontal mapreduce