From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Fri, 30 Aug 2019 12:22:46 +0000 (+0300)
Subject: Fix macc test
X-Git-Tag: working-ls180~1084^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17c92dc679458a9ffabd76e2ce8e2491bd249110;p=yosys.git

Fix macc test
---

diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
index 233e7e890..d65c31b73 100644
--- a/tests/ice40/macc.ys
+++ b/tests/ice40/macc.ys
@@ -4,7 +4,7 @@ hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 41 t:SB_LUT4
+select -assert-count 38 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-count 7 t:SB_DFFSR
 select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D