From: Eddie Hung Date: Sun, 17 Feb 2019 19:49:06 +0000 (-0800) Subject: Merge https://github.com/YosysHQ/yosys into dff_init X-Git-Tag: yosys-0.9~313^2~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17cd5f759f74b3f2b96d2035970ebac03509df9a;p=yosys.git Merge https://github.com/YosysHQ/yosys into dff_init --- 17cd5f759f74b3f2b96d2035970ebac03509df9a diff --cc tests/tools/autotest.sh index 800fa3ad5,218edf931..6fdd1e80a --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@@ -22,7 -28,7 +28,7 @@@ if [ ! -f $toolsdir/cmp_tbdata -o $tool ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi - while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do -while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do ++while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do case "$opt" in x) use_xsim=true ;; @@@ -59,10 -65,24 +65,26 @@@ include_opts="$include_opts -I $OPTARG" xinclude_opts="$xinclude_opts -i $OPTARG" minclude_opts="$minclude_opts +incdir+$OPTARG" ;; + B) + backend_opts="$backend_opts $OPTARG" ;; + -) + case "${OPTARG}" in + xfirrtl) + xfirrtl="${!OPTIND}" + OPTIND=$(( $OPTIND + 1 )) + ;; + firrtl2verilog) + firrtl2verilog="${!OPTIND}" + OPTIND=$(( $OPTIND + 1 )) + ;; + *) + if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then + echo "Unknown option --${OPTARG}" >&2 + fi + ;; + esac;; *) - echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] verilog-files\n" >&2 - echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2 ++ echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2 exit 1 esac done