From: Andreas Krebbel Date: Tue, 26 Sep 2017 10:35:53 +0000 (+0000) Subject: S/390: Fix vmslg instruction and builtin. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17ec4b792b8a5c8b454928efe409f62c4e356ffe;p=gcc.git S/390: Fix vmslg instruction and builtin. gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vx-builtins.md ("vmslg"): Add missing operand in assembler output. * config/s390/s390-builtins.def: Fix constraint on op4. From-SVN: r253198 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 430b08b6e10..87801a43cc3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-09-26 Andreas Krebbel + + * config/s390/vx-builtins.md ("vmslg"): Add missing operand in + assembler output. + * config/s390/s390-builtins.def: Fix constraint on op4. + 2017-09-26 Andreas Krebbel * config/s390/s390.c (s390_expand_vec_compare): Use the new mode diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index ddcf370cb23..3f7bae7ca56 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -2271,7 +2271,7 @@ OB_DEF_VAR (s390_vec_test_mask_dbl, s390_vtm, 0, B_DEF (s390_vtm, vec_test_mask_intv16qi,0, B_VX, 0, BT_FN_INT_UV16QI_UV16QI) B_DEF (s390_vec_msum_u128, vec_msumv2di, 0, B_VXE, O4_U2, BT_FN_UV16QI_UV2DI_UV2DI_UV16QI_INT) -B_DEF (s390_vmslg, vmslg, 0, B_VXE, O4_U2, BT_FN_INT128_UV2DI_UV2DI_INT128_INT) +B_DEF (s390_vmslg, vmslg, 0, B_VXE, O4_U4, BT_FN_INT128_UV2DI_UV2DI_INT128_INT) OB_DEF (s390_vec_eqv, s390_vec_eqv_b8, s390_vec_eqv_dbl_c, B_VXE, BT_FN_OV4SI_OV4SI_OV4SI) OB_DEF_VAR (s390_vec_eqv_b8, s390_vnx, 0, 0, BT_OV_BV16QI_BV16QI_BV16QI) diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 4c157e32efb..7fb176c2fa4 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -1190,7 +1190,7 @@ (match_operand:QI 4 "const_mask_operand" "C")] UNSPEC_VEC_MSUM))] "TARGET_VXE" - "vmslg\t%v0,%v1,%v2,%v3" + "vmslg\t%v0,%v1,%v2,%v3,%4" [(set_attr "op_type" "VRR")]) (define_insn "vmslg" @@ -1201,7 +1201,7 @@ (match_operand:QI 4 "const_mask_operand" "C")] UNSPEC_VEC_MSUM))] "TARGET_VXE" - "vmslg\t%v0,%v1,%v2,%v3" + "vmslg\t%v0,%v1,%v2,%v3,%4" [(set_attr "op_type" "VRR")])