From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 18 Mar 2013 17:45:19 +0000 (+0100)
Subject: fhdl/verilog: optionally disable clock domain creation
X-Git-Tag: 24jan2021_ls180~2099^2~632
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17f2b176541ea34fee2c6e7bfc37eea095127994;p=litex.git

fhdl/verilog: optionally disable clock domain creation
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 0c873ca0..10e17291 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -258,6 +258,7 @@ def _printinit(f, ios, ns):
 def convert(f, ios=None, name="top",
   return_ns=False,
   special_overrides=dict(),
+  create_clock_domains=True,
   display_run=False):
 	if not isinstance(f, Fragment):
 		f = f.get_fragment()
@@ -268,9 +269,12 @@ def convert(f, ios=None, name="top",
 		try:
 			f.clock_domains[cd_name]
 		except KeyError:
-			cd = ClockDomain(cd_name)
-			f.clock_domains.append(cd)
-			ios |= {cd.clk, cd.rst}
+			if create_clock_domains:
+				cd = ClockDomain(cd_name)
+				f.clock_domains.append(cd)
+				ios |= {cd.clk, cd.rst}
+			else:
+				raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 	
 	_insert_resets(f)
 	f = lower_basics(f)