From: Korey Sewell <ksewell@umich.edu>
Date: Mon, 20 Jun 2011 01:43:34 +0000 (-0400)
Subject: inorder: ISA-zero reg handling
X-Git-Tag: stable_2012_02_02~261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17f5749dbbb007ee56b60c27f15f43e2e5250408;p=gem5.git

inorder: ISA-zero reg handling
ignore writes to the ISA zero register
---

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 01eab9af7..f1c531c53 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1135,10 +1135,16 @@ InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
 void
 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
 {
-    DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
-            tid, reg_idx, val);
+    if (reg_idx == TheISA::ZeroReg) {
+        DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
+                "(Int. Reg %i) to %x\n", tid, reg_idx, val);
+        return;
+    } else {
+        DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
+                tid, reg_idx, val);
 
-    intRegs[tid][reg_idx] = val;
+        intRegs[tid][reg_idx] = val;
+    }
 }