From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Mar 2019 15:06:48 +0000 (+0000)
Subject: synchronisation of mid is not working
X-Git-Tag: ls180-24jan2020~1495
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=17f7e138c7508ffaf8873266f80feed58d22e6b2;p=ieee754fpu.git

synchronisation of mid is not working
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 7f70af6f..97ee057b 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -577,23 +577,30 @@ class UnbufferedPipeline(PipelineBase):
             n_i_readyn = Array(n_i_readyn)
             data_valid = Array(data_valid)
 
-        ni = 0 # TODO: use n_nux to decide which to select
+        ni = 0 # TODO: use n_mux to decide which to select
 
         if self.p_mux:
             mid = self.p_mux.m_id
             for i in range(p_len):
+                m.d.sync += data_valid[i].eq(0)
+                m.d.comb += n_i_readyn[i].eq(1)
                 m.d.comb += p_i_valid[i].eq(0)
                 m.d.comb += self.p[i].o_ready.eq(0)
             m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
             m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | \
                                               self.n[ni].i_ready)
-            m.d.comb += self.n[ni].o_valid.eq(data_valid[mid])
+            m.d.comb += n_i_readyn[mid].eq(~self.n[ni].i_ready & \
+                                          data_valid[mid])
+            anyvalid = Signal(i, reset_less=True)
+            av = []
+            for i in range(p_len):
+                av.append(data_valid[i])
+            anyvalid = Cat(*av)
+            m.d.comb += self.n[ni].o_valid.eq(anyvalid.bool())
+            m.d.sync += data_valid[mid].eq(p_i_valid[mid] | \
+                                        (n_i_readyn[mid] & data_valid[mid]))
 
             for i in range(p_len):
-                m.d.comb += n_i_readyn[i].eq(~self.n[ni].i_ready & \
-                                              data_valid[i])
-                m.d.sync += data_valid[i].eq(p_i_valid[i] | \
-                                            (n_i_readyn[i] & data_valid[i]))
                 with m.If(self.p[i].i_valid & self.p[i].o_ready):
                     m.d.sync += eq(r_data[i], self.p[i].i_data)
 
diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index c1af8045..d5f67310 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -175,28 +175,28 @@ class InputTest:
             self.di[mid] = {}
             self.do[mid] = {}
             for i in range(self.tlen):
-                self.di[mid][i] = randint(0, 100)
+                self.di[mid][i] = randint(0, 100) + (mid<<8)
                 self.do[mid][i] = self.di[mid][i]
 
     def send(self, mid):
         for i in range(self.tlen):
             op2 = self.di[mid][i]
             rs = dut.p[mid]
-            yield rs.i_valid.eq(0)
+            yield rs.i_valid.eq(1)
             o_p_ready = yield rs.o_ready
             while not o_p_ready:
                 yield
                 o_p_ready = yield rs.o_ready
 
-            print ("send", mid, i, op2)
+            print ("send", mid, i, hex(op2))
 
-            yield rs.i_valid.eq(1)
             yield rs.i_data.data.eq(op2)
             yield rs.i_data.idx.eq(i)
             yield rs.i_data.mid.eq(mid)
             #for v in self.dut.set_input((op2, i, mid)):
             #    yield v
             yield
+            yield rs.i_valid.eq(0)
 
         yield rs.i_valid.eq(0)
         ## wait random period of time before queueing another value
@@ -228,7 +228,7 @@ class InputTest:
             out_i = yield n.o_data.idx
             out_v = yield n.o_data.data
 
-            print ("recv", mid, out_i, out_v)
+            print ("recv", mid, out_i, hex(out_v))
 
             # see if this output has occurred already, delete it if it has
             assert out_i in self.do[mid], "out_i %d not in array %s" % \