From: whitequark <cz@m-labs.hk>
Date: Wed, 26 Dec 2018 09:45:12 +0000 (+0000)
Subject: hdl.dsl: add signal decoder to FSM state signal.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=180307d06af7abf5e31d01030356a842a00b01ab;p=nmigen.git

hdl.dsl: add signal decoder to FSM state signal.
---

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index cc16d16..7a531a7 100644
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -298,6 +298,8 @@ class Module(_ModuleBuilderRoot):
             fsm_signal, fsm_encoding, fsm_states = data["signal"], data["encoding"], data["states"]
             fsm_signal.nbits = bits_for(len(fsm_encoding) - 1)
             # The FSM is encoded such that the state with encoding 0 is always the reset state.
+            fsm_decoding = {n: s for s, n in fsm_encoding.items()}
+            fsm_signal.decoder = lambda v: "{}/{}".format(fsm_decoding[n], n)
             self._statements.append(Switch(fsm_signal,
                 OrderedDict((fsm_encoding[name], stmts) for name, stmts in fsm_states.items())))