From: Miodrag Milanović <mmicko@gmail.com>
Date: Wed, 25 Nov 2020 18:15:11 +0000 (+0100)
Subject: Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments
X-Git-Tag: working-ls180~188
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=180a8e5a45358b4d2c9b599e6838093fd121f9fd;p=yosys.git

Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments

Generate only simple assignments in verilog backend
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180a8e5a45358b4d2c9b599e6838093fd121f9fd