From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 16 Dec 2006 12:10:58 +0000 (-0500)
Subject: Made changes to CWP be non speculative.
X-Git-Tag: m5_2.0_beta3~274^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=181f4f32f6a2ffd19700e54cd5581fce19ec04a5;p=gem5.git

Made changes to CWP be non speculative.

--HG--
extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
---

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 9a5fda6ff..256f2fa43 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -123,7 +123,7 @@ def operands {{
     'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
     'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 60),
     'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
-    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing']), 62),
+    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
 #   'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
 #   'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
 #   'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),