From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 23:40:30 +0000 (-0700)
Subject: xaiger: promote abc9_keep wires
X-Git-Tag: working-ls180~512^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1826370b3ab1485f966a796b95860779ae1dbd69;p=yosys.git

xaiger: promote abc9_keep wires
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 6b910eecd..4a8f54c4d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -156,7 +156,7 @@ struct XAigerWriter
 
 		// promote keep wires
 		for (auto wire : module->wires())
-			if (wire->get_bool_attribute(ID::keep))
+			if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep))
 				sigmap.add(wire);
 
 		for (auto wire : module->wires()) {