From: whitequark <whitequark@whitequark.org>
Date: Fri, 21 Dec 2018 01:26:08 +0000 (+0000)
Subject: manual: make description of $meminit ports match reality.
X-Git-Tag: yosys-0.9~360^2^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=182d84ad54cff315e7afb07f5353a477e4c410f4;p=yosys.git

manual: make description of $meminit ports match reality.
---

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 65a79020f..d40a600ed 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -274,13 +274,25 @@ edge if this parameter is {\tt 1'b0}.
 The cell with the higher integer value in this parameter wins a write conflict.
 \end{itemize}
 
-The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}. Both of the inputs
-must resolve to a constant for synthesis to succeed. If two {\tt \$meminit} cells have the same
-\B{MEMID} parameter and \B{ADDR} input, the contents of that memory at that address is undefined.
+The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}, with the width
+of the \B{DATA} port equal to \B{WIDTH} parameter times \B{WORDS} parameter. Both of the inputs
+must resolve to a constant for synthesis to succeed.
 
 \begin{itemize}
 \item \B{MEMID} \\
 The name of the RTLIL::Memory object that is associated with this initialization cell.
+
+\item \B{ABITS} \\
+The number of address bits (width of the \B{ADDR} input port).
+
+\item \B{WIDTH} \\
+The number of data bits per memory location.
+
+\item \B{WORDS} \\
+The number of consecutive memory locations initialized by this cell.
+
+\item \B{PRIORITY} \\
+The cell with the higher integer value in this parameter wins an initialization conflict.
 \end{itemize}
 
 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous