From: WRansohoff <WRansohoff@users.noreply.github.com>
Date: Mon, 23 Mar 2020 01:14:44 +0000 (-0400)
Subject: Add Upduino v1/v2.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18315d8efc4b2d0569ff1abf19a92f495de7745d;p=nmigen-boards.git

Add Upduino v1/v2.
---

diff --git a/nmigen_boards/upduino_v1.py b/nmigen_boards/upduino_v1.py
new file mode 100644
index 0000000..6790450
--- /dev/null
+++ b/nmigen_boards/upduino_v1.py
@@ -0,0 +1,36 @@
+from nmigen.build import *
+from nmigen.vendor.lattice_ice40 import *
+from .resources import *
+
+
+__all__ = ["UpduinoV1Platform"]
+
+
+class UpduinoV1Platform(LatticeICE40Platform):
+    device      = "iCE40UP5K"
+    package     = "SG48"
+    default_clk = "SB_HFOSC"
+    hfosc_div   = 0
+    resources   = [
+        *LEDResources(pins="39 40 41", invert=True,
+                      attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
+        Resource("led_g", 0, PinsN("39", dir="o"),
+                 Attrs(IO_STANDARD="SB_LVCMOS")),
+        Resource("led_b", 0, PinsN("40", dir="o"),
+                 Attrs(IO_STANDARD="SB_LVCMOS")),
+        Resource("led_r", 0, PinsN("41", dir="o"),
+                 Attrs(IO_STANDARD="SB_LVCMOS")),
+
+        *SPIFlashResources(0,
+            cs="16", clk="15", miso="17", mosi="14",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS")
+        ),
+    ]
+    connectors  = [
+        # "Left" row of header pins (JP5 on the schematic)
+        Connector("j", 0, "- - 23 25 26 27 32 35 31 37 34 43 36 42 38 28"),
+        # "Right" row of header pins (JP6 on the schematic)
+        Connector("j", 1, "12 21 13 19 18 11 9 6 44 4 3 48 45 47 46 2")
+    ]
+
+    # This board doesn't have an integrated programmer.
diff --git a/nmigen_boards/upduino_v2.py b/nmigen_boards/upduino_v2.py
new file mode 100644
index 0000000..aebb04c
--- /dev/null
+++ b/nmigen_boards/upduino_v2.py
@@ -0,0 +1,30 @@
+import os
+import subprocess
+
+from nmigen.build import *
+from nmigen.vendor.lattice_ice40 import *
+from .resources import *
+from .upduino_v1 import UpduinoV1Platform
+
+
+__all__ = ["UpduinoV2Platform"]
+
+
+class UpduinoV2Platform(UpduinoV1Platform):
+    # Mostly identical to the V1 board, but it has an integrated
+    # programmer and a 12MHz oscillator which is NC by default.
+    resources = UpduinoV1Platform.resources + [
+        # Solder pin 12 to the adjacent 'J8' osc_out pin to enable.
+        Resource("clk12", 0, Pins("12", dir="i"),
+                 Clock(12e6), Attrs(IO_STANDARD="SB_LVCMOS")),
+    ]
+
+    def toolchain_program(self, products, name):
+        iceprog = os.environ.get("ICEPROG", "iceprog")
+        with products.extract("{}.bin".format(name)) as bitstream_filename:
+            subprocess.check_call([iceprog, bitstream_filename])
+
+
+if __name__ == "__main__":
+    from .test.blinky import *
+    UpduinoV2Platform().build(Blinky(), do_program=True)