From: whitequark <whitequark@whitequark.org>
Date: Mon, 7 Dec 2020 09:24:35 +0000 (+0000)
Subject: bugpoint: add -wires option.
X-Git-Tag: working-ls180~171^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1838edf35cbd558d3a9a9c4a1ea10e080e8d56ab;p=yosys.git

bugpoint: add -wires option.
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a9f585616..1faf376e7 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1826,7 +1826,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 			sig.pack();
 			for (auto &c : sig.chunks_)
 				if (c.wire != NULL && wires_p->count(c.wire)) {
-					c.wire = module->addWire(NEW_ID, c.width);
+					c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
 					c.offset = 0;
 				}
 		}
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index f2d70a3d1..da81e7f09 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -136,7 +136,7 @@ struct BugpointPass : public Pass {
 		return design_copy;
 	}
 
-	RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool processes, bool assigns, bool updates)
+	RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool processes, bool assigns, bool updates, bool wires)
 	{
 		RTLIL::Design *design_copy = new RTLIL::Design;
 		for (auto module : design->modules())
@@ -343,6 +343,35 @@ struct BugpointPass : public Pass {
 				}
 			}
 		}
+		if (wires)
+		{
+			for (auto mod : design_copy->modules())
+			{
+				if (mod->get_blackbox_attribute())
+					continue;
+
+				Wire *removed_wire = nullptr;
+				for (auto wire : mod->wires())
+				{
+					if (wire->get_bool_attribute(ID::bugpoint_keep))
+						continue;
+
+					if (wire->name.begins_with("$delete_wire"))
+						continue;
+
+					if (index++ == seed)
+					{
+						log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire));
+						removed_wire = wire;
+						break;
+					}
+				}
+				if (removed_wire) {
+					mod->remove({removed_wire});
+					return design_copy;
+				}
+			}
+		}
 		return nullptr;
 	}
 
@@ -350,7 +379,7 @@ struct BugpointPass : public Pass {
 	{
 		string yosys_cmd = "yosys", yosys_arg, grep;
 		bool fast = false, clean = false;
-		bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, has_part = false;
+		bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false;
 
 		log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
 		log_push();
@@ -421,6 +450,11 @@ struct BugpointPass : public Pass {
 				has_part = true;
 				continue;
 			}
+			if (args[argidx] == "-wires") {
+				wires = true;
+				has_part = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -437,6 +471,7 @@ struct BugpointPass : public Pass {
 			processes = true;
 			assigns = true;
 			updates = true;
+			wires = true;
 		}
 
 		if (!design->full_selection())
@@ -452,7 +487,7 @@ struct BugpointPass : public Pass {
 		bool found_something = false, stage2 = false;
 		while (true)
 		{
-			if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, processes, assigns, updates))
+			if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, processes, assigns, updates, wires))
 			{
 				simplified = clean_design(simplified, fast, /*do_delete=*/true);