From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 12 Aug 2012 14:04:52 +0000 (+0200)
Subject: add simple Sequencer
X-Git-Tag: 24jan2021_ls180~2575^2~180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18452c8193b9823f02b5449e941b01a19ad4a156;p=litex.git

add simple Sequencer
---

diff --git a/migScope/__init__.py b/migScope/__init__.py
index 69675d75..7c4993f8 100644
--- a/migScope/__init__.py
+++ b/migScope/__init__.py
@@ -228,6 +228,7 @@ class Recorder:
 		#Control
 		self.rst = Signal()
 		self.start = Signal()
+		self.offset = Signal(BV(self.depth_width))
 		self.size = Signal(BV(self.depth_width))
 		self.done = Signal()
 		#Write Path
@@ -245,10 +246,14 @@ class Recorder:
 		#Others
 		self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
 		
+		
 	def get_fragment(self):
 		comb = []
 		sync = []
 		memories = [self._mem]
+		size_minus_offset = Signal(BV(self.depth_width))
+		comb += [size_minus_offset.eq(self.size-self.offset)]
+		
 		#Control
 		sync += [
 			If(self.rst,
@@ -259,7 +264,8 @@ class Recorder:
 				self.done.eq(0)
 			).Elif(self.start,
 				self._put_cnt.eq(0),
-				self._get_cnt.eq(0)
+				self._get_cnt.eq(0),
+				self._get_ptr.eq(self._put_ptr-size_minus_offset)
 			),
 			If(self.put,
 				self._put_cnt.eq(self._put_cnt+1),
@@ -271,15 +277,53 @@ class Recorder:
 			)
 			]
 		comb += [
-			If(self._put_cnt == self.size-1,
+			If(self._put_cnt == size_minus_offset-1,
 				self.done.eq(1)
-			).Elif(self._get_cnt == self.size-1,
+			).Elif(self._get_cnt == size_minus_offset-1,
 				self.done.eq(1)
 			).Else(
 				self.done.eq(0)
 			)
 			]
 		return Fragment(comb=comb, sync=sync, memories=memories)
+		
+class Sequencer:
+	def __init__(self,depth):
+		self.depth = depth
+		self.depth_width = bits_for(self.depth)
+		# Controller interface
+		self.ctl_rst = Signal()
+		self.ctl_offset = Signal(BV(self.depth_width))
+		self.ctl_arm = Signal()
+		self.ctl_done = Signal()
+		# Triggers interface
+		self.trig_hit  = Signal()
+		# Recorder interface
+		self.rec_offset = Signal(BV(self.depth_width))
+		self.rec_start = Signal()
+		self.rec_done  = Signal()
+		# Others
+		self.enable = Signal()
+		
+	def get_fragment(self):
+		comb = []
+		sync = []
+		#Control
+		sync += [
+			If(self.ctl_rst,
+				self.enable.eq(0)
+			).Elif(self.ctl_arm,
+				self.enable.eq(1)
+			).Elif(self.rec_done,
+				self.enable.eq(0)
+			)
+			]
+		comb += [
+			self.rec_offset.eq(self.ctl_offset),
+			self.rec_start.eq(self.enable & self.trig_hit)
+			]
+		return Fragment(comb=comb, sync=sync)
+
 
 class MigCon:
 	pass
diff --git a/top.py b/top.py
index addf0a4c..b6afc282 100644
--- a/top.py
+++ b/top.py
@@ -38,9 +38,9 @@ import migScope
 #
 #Test Sum
 #
-sum = migScope.Sum(4,pipe=True)
-v = verilog.convert(sum.get_fragment())
-print(v)
+#sum = migScope.Sum(4,pipe=True)
+#v = verilog.convert(sum.get_fragment())
+#print(v)
 
 #
 #Test MigIo
@@ -54,4 +54,11 @@ print(v)
 #
 #recorder = migScope.Recorder(32,1024)
 #v = verilog.convert(recorder.get_fragment())
-#print(v)
\ No newline at end of file
+#print(v)
+
+#
+#Test Sequencer
+#
+sequencer = migScope.Sequencer(1024)
+v = verilog.convert(sequencer.get_fragment())
+print(v)
\ No newline at end of file