From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 17:32:07 +0000 (+0100)
Subject: set SPRs inside qemu run_program
X-Git-Tag: xlen-bcd~524
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1848a7331a87beb8ca83fca343d7d17afbb165e6;p=openpower-isa.git

set SPRs inside qemu run_program
---

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 50d6024e..5a4d3e6d 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -88,8 +88,8 @@ def read_entries(fname, listqty=None):
 
     return result
 
-def qemu_register_compare(sim, qemu, regs, fprs):
-    qpc, qxer, qcr = qemu.get_pc(), qemu.get_xer(), qemu.get_cr()
+def qemu_register_compare(sim, q, regs, fprs):
+    qpc, qxer, qcr, qlr = q.get_pc(), q.get_xer(), q.get_cr(), q.get_lr()
     sim_cr = sim.cr.value
     sim_pc = sim.pc.CIA.value
     sim_xer = sim.spr['XER'].value
@@ -102,14 +102,14 @@ def qemu_register_compare(sim, qemu, regs, fprs):
     print("sim xer", hex(sim_xer))
     #self.assertEqual(qpc, sim_pc)
     for reg in regs:
-        qemu_val = qemu.get_gpr(reg)
+        qemu_val = q.get_gpr(reg)
         sim_val = sim.gpr(reg).value
         if qemu_val != sim_val:
             log("expect gpr %d %x got %x" % (reg, qemu_val, sim_val))
         #self.assertEqual(qemu_val, sim_val,
         #                 "expect %x got %x" % (qemu_val, sim_val))
     for fpr in fprs:
-        qemu_val = qemu.get_fpr(fpr)
+        qemu_val = q.get_fpr(fpr)
         sim_val = sim.fpr(fpr).value
         if qemu_val != sim_val:
             log("expect fpr %d %x got %x" % (fpr, qemu_val, sim_val))
@@ -133,14 +133,7 @@ def run_tst(args, generator, qemu,
         log("qemu program", generator.binfile.name)
         qemu = run_program(generator, initial_mem=mem, 
                 bigendian=False, start_addr=initial_pc,
-                continuous_run=False)
-        # TODO: SPRs.  how?? sigh, by cheating
-        if initial_sprs:
-            lr = initial_sprs.get('lr', None)
-            if lr is None:
-                lr = initial_sprs.get('LR', None)
-            if lr is not None:
-                qemu.set_lr(lr)
+                continuous_run=False, initial_sprs=initial_sprs)
         if initial_regs is not None:
             for reg, val in enumerate(initial_regs):
                 qemu.set_gpr(reg, val)
diff --git a/src/openpower/simulator/qemu.py b/src/openpower/simulator/qemu.py
index 28042d0b..2f77b9fc 100644
--- a/src/openpower/simulator/qemu.py
+++ b/src/openpower/simulator/qemu.py
@@ -218,7 +218,7 @@ class QemuController:
 
 def run_program(program, initial_mem=None, extra_break_addr=None,
                 bigendian=False, start_addr=0x20000000, init_endian=True,
-                continuous_run=True):
+                continuous_run=True, initial_sprs=None):
     q = QemuController(program.binfile.name, bigendian)
     q.connect()
     q.set_endian(init_endian)  # easier to set variables this way
@@ -246,6 +246,15 @@ def run_program(program, initial_mem=None, extra_break_addr=None,
     q.set_cr(0)
     # delete the previous breakpoint so loops don't screw things up
     q.delete_breakpoint()
+
+    # can't do many of these - lr, ctr, etc. etc. later, just LR for now
+    if initial_sprs:
+        lr = initial_sprs.get('lr', None)
+        if lr is None:
+            lr = initial_sprs.get('LR', None)
+        if lr is not None:
+            q.set_lr(lr)
+
     # allow run to end
     q.break_address(start_addr + program.size())
     # or to trap (not ideal)