From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 19 Sep 2015 15:21:24 +0000 (+0800)
Subject: fhdl/specials: MemoryPort.clock should always be a ClockSignal
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1861ae9d01d8c9c6ccd84c95683c30d459510da3;p=litex.git

fhdl/specials: MemoryPort.clock should always be a ClockSignal
---

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index e4bc6060..4137d746 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -193,10 +193,7 @@ class _MemoryPort(Special):
         self.re = re
         self.we_granularity = we_granularity
         self.mode = mode
-        if isinstance(clock_domain, str):
-            self.clock = ClockSignal(clock_domain)
-        else:
-            self.clock = clock_domain
+        self.clock = ClockSignal(clock_domain)
 
     def iter_expressions(self):
         for attr, target_context in [