From: Richard Sandiford <richard.sandiford@arm.com>
Date: Tue, 30 Nov 2021 17:50:24 +0000 (+0000)
Subject: aarch64: Mark PMSIDR_EL1 as read-only
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1864b6578bd96bee057ed4ce5f69917c9ad9abc9;p=binutils-gdb.git

aarch64: Mark PMSIDR_EL1 as read-only

We were incorrectly allowing writes to PMSIDR_EL1, which is
a read-only register.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/PMSIDR-EL1--Sampling-Profiling-ID-Register?lang=en]

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Make pmsidr_el1 as F_REG_READ.

gas/
	* testsuite/gas/aarch64/msr.s: Remove write to pmsidr_el1.
	* testsuite/gas/aarch64/msr.d: Update accordingly.
	* testsuite/gas/aarch64/illegal-sysreg-2.s,
	* testsuite/gas/aarch64/illegal-sysreg-2.d,
	* testsuite/gas/aarch64/illegal-sysreg-2.l: New test.
---

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-2.d b/gas/testsuite/gas/aarch64/illegal-sysreg-2.d
new file mode 100644
index 00000000000..bff7ea7d20d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-2.d
@@ -0,0 +1,2 @@
+#source: illegal-sysreg-2.s
+#warning_output: illegal-sysreg-2.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-2.l b/gas/testsuite/gas/aarch64/illegal-sysreg-2.l
new file mode 100644
index 00000000000..60aa5c26ad9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-2.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr pmsidr_el1,x0'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-2.s b/gas/testsuite/gas/aarch64/illegal-sysreg-2.s
new file mode 100644
index 00000000000..f95584cc56b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-2.s
@@ -0,0 +1,3 @@
+/* Write to R/O system registers.  */
+.arch armv8.2-a+profile
+msr pmsidr_el1, x0
diff --git a/gas/testsuite/gas/aarch64/msr.d b/gas/testsuite/gas/aarch64/msr.d
index 4d5e630921a..fedf2eecd0d 100644
--- a/gas/testsuite/gas/aarch64/msr.d
+++ b/gas/testsuite/gas/aarch64/msr.d
@@ -24,5 +24,4 @@ Disassembly of section \.text:
   3c:	d5300040 	mrs	x0, osdtrrx_el1
   40:	d5100340 	msr	osdtrtx_el1, x0
   44:	d5300340 	mrs	x0, osdtrtx_el1
-  48:	d51899e0 	msr	pmsidr_el1, x0
-  4c:	d53899e0 	mrs	x0, pmsidr_el1
+  48:	d53899e0 	mrs	x0, pmsidr_el1
diff --git a/gas/testsuite/gas/aarch64/msr.s b/gas/testsuite/gas/aarch64/msr.s
index 5e8ae850004..36ebfe441f4 100644
--- a/gas/testsuite/gas/aarch64/msr.s
+++ b/gas/testsuite/gas/aarch64/msr.s
@@ -47,5 +47,4 @@ func:
 	msr osdtrtx_el1, x0
 	mrs x0, osdtrtx_el1
 
-	msr pmsidr_el1, x0
 	mrs x0, pmsidr_el1
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 714c705ea91..372101a86a7 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4346,7 +4346,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_PROFILE ("pmsfcr_el1",	CPENC (3,0,C9,C9,4),	0),
   SR_PROFILE ("pmsevfr_el1",	CPENC (3,0,C9,C9,5),	0),
   SR_PROFILE ("pmslatfr_el1",	CPENC (3,0,C9,C9,6),	0),
-  SR_PROFILE ("pmsidr_el1",	CPENC (3,0,C9,C9,7),	0),
+  SR_PROFILE ("pmsidr_el1",	CPENC (3,0,C9,C9,7),	F_REG_READ),
   SR_PROFILE ("pmscr_el2",	CPENC (3,4,C9,C9,0),	0),
   SR_PROFILE ("pmscr_el12",	CPENC (3,5,C9,C9,0),	0),
   SR_CORE ("pmcr_el0",		CPENC (3,3,C9,C12,0),	0),