From: Anton Blanchard Date: Mon, 9 Aug 2021 03:02:01 +0000 (+1000) Subject: Remove -waveform from xdc files X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=187199c489993841a73727381edaffc957973db4;p=microwatt.git Remove -waveform from xdc files A 50% duty cycle is the default, so no need to use -waveform. Signed-off-by: Anton Blanchard --- diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 64e0405..309b12f 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -531,7 +531,7 @@ set_property CONFIG_MODE SPIx4 [current_design] # Clock constraints ################################################################################ -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; +create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }] diff --git a/fpga/cmod_a7-35.xdc b/fpga/cmod_a7-35.xdc index 3492d54..4444e2a 100644 --- a/fpga/cmod_a7-35.xdc +++ b/fpga/cmod_a7-35.xdc @@ -1,6 +1,6 @@ ## Clock signal 12 MHz set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; -create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {ext_clk}]; +create_clock -add -name sys_clk_pin -period 83.33 [get_ports {ext_clk}]; set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; diff --git a/fpga/genesys2.xdc b/fpga/genesys2.xdc index 826e5f4..967a168 100644 --- a/fpga/genesys2.xdc +++ b/fpga/genesys2.xdc @@ -3,8 +3,8 @@ ## Clock & Reset set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { clk200_n }] set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { clk200_p }] -create_clock -period 5.000 -name tc_clk100_p -waveform {0.000 2.500} [get_ports clk200_p] -create_clock -period 5.000 -name tc_clk100_n -waveform {2.500 5.000} [get_ports clk200_n] +create_clock -period 5.000 -name tc_clk100_p [get_ports clk200_p] +create_clock -period 5.000 -name tc_clk100_n [get_ports clk200_n] set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }] diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc index 85c7331..6a46627 100644 --- a/fpga/nexys-video.xdc +++ b/fpga/nexys-video.xdc @@ -313,7 +313,7 @@ set_property CONFIG_MODE SPIx4 [current_design] # Clock constraints ################################################################################ -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; +create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; ################################################################################ # False path constraints (from LiteX as they relate to LiteDRAM) diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc index a572772..aa1af22 100644 --- a/fpga/nexys_a7.xdc +++ b/fpga/nexys_a7.xdc @@ -1,5 +1,5 @@ set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk] -create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk] +create_clock -period 10.000 -name sys_clk_pin -add [get_ports ext_clk] set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]